MIC2588/MIC2594
Micrel
MIC2588/MIC2594
Single-Channel, Negative High-Voltage Hot
Swap Power Controllers
General Description
The MIC2588 and the MIC2594 are single-channel, nega-
tive-voltage hot swap controllers designed to address the
need for safe insertion and removal of circuit boards into
“live” high-voltage system backplanes, while using very few
external components. The MIC2588 and the MIC2594 are
each available in an 8-pin SOIC package and work in con-
junction with an external N-Channel MOSFET for which the
gate drive is controlled to provide inrush current limiting and
output voltage slew-rate control. Overcurrent fault protection
is also provided and includes a programmable overcurrent
threshold. During an output overload condition, a constant-
current regulation loop is engaged to ensure that the system
power supply maintains regulation. If a fault condition exceeds
a built-in 400µs nuisance-trip delay, the MIC2588 and the
MIC2594 will latch the circuit breaker’s output off and will
remain in the off state until reset by cycling either the UV/OFF
pin or the power to the IC. A master Power-Good signal is
provided to indicate that the output voltage of the soft-start
circuit is within its valid output range. This signal can be used
to enable one or more DC-DC converter modules.
All support documentation can be found on Micrel’s web site
at www.micrel.com.
Features
• MIC2588:
Pin-for-pin functional equivalent to the
LT1640/LT1640A/LT4250
• Provides safe insertion and removal from live –48V
(nominal) backplanes
• Operates from –19V to –80V
• Electronic circuit breaker function
• Built-in 400µs “nuisance-trip” delay (t
FLT
)
• Regulated maximum output current into faults
• Programmable inrush current limiting
• Fast response to short circuit conditions (< 1µs)
• Programmable undervoltage and overvoltage lockouts
(MIC2588-xBM)
• Programmable UVLO hysteresis (MIC2594-xBM)
• Fault reporting:
Active-HIGH (-1BM) and Active-LOW (-2BM)
Power-Good output signal
Applications
•
•
•
•
Central office switching
–48V power distribution
Distributed power systems
Server Networks
Typical Application
-48V RTN
(Long Pin)
-48V RTN
DC-DC
CONVERTER
1
/PWRGD
VDD
8
IN+
C5
100uF
C4
0.1uF
OUT+
+2.5V
OUT
*D1
SMAT70A
100V
ON/OFF
#
IN-
2
-48V RTN
(Short Pin)
R1
698kΩ
1%
R2
11.8kΩ
1%
OV
DRAIN
7
OUT-
MIC2588-2BM
3
UV
GATE
+2.5V RTN
6
R3
12.4kΩ
1%
4
VEE
SENSE
5
*C2
22nF
R
FDBK
15kΩ
C
FDBK
6.8nF
100V
C1
1uF
VDD
*C6
0.33uF
R4
10Ω
C3
0.22uF
-48V
IN
(Long Pin)
R
SENSE
0.01Ω
5%
-48V
OUT
M1
SUM110N10-09
Nominal Undervoltage and Overvoltage Thresholds:
V
UV
= 36.5V
V
OV
= 71.2V
* Optional components (See Applications Information for more details)
# An external pull-up resistor for the power-good signal is necessary for DC-DC supplies
(and all other load modules) not equipped with internal pull-up impedence
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 2005
1
M9999-083005
MIC2588/MIC2594
Micrel
Ordering Information
Part Number
Standard
MIC2588-1BM
MIC2588-2BM
MIC2594-1BM
MIC2594-2BM
Pb-Free
MIC2588-1YM
MIC2588-2YM
MIC2594-1YM
MIC2594-2YM
PWRGD Polarity
Active-High
Active-Low
Active-High
Active-Low
Lockout Functions
Undervoltage and
Overvoltage
Undervoltage and
Overvoltage
Programmable UVLO
Hysteresis
Programmable UVLO
Hysteresis
Circuit Breaker
Function
Latched Off
Latched Off
Latched Off
Latched Off
Package
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
Pin Configuration
PWRGD 1
OV 2
UV 3
VEE 4
8 VDD
7 DRAIN
6 GATE
5 SENSE
/PWRGD 1
OV 2
UV 3
VEE 4
8 VDD
7 DRAIN
6 GATE
5 SENSE
8-Pin SOIC (M)
MIC2588-1BM
8-Pin SOIC (M)
MIC2588-2BM
8 VDD
7 DRAIN
6 GATE
5 SENSE
PWRGD 1
ON 2
OFF 3
VEE 4
/PWRGD 1
ON 2
OFF 3
VEE 4
8 VDD
7 DRAIN
6 GATE
5 SENSE
8-Pin SOIC (M)
MIC2594-1BM
8-Pin SOIC (M)
MIC2594-2BM
M9999-083005
2
September 2005
MIC2588/MIC2594
Micrel
Pin Name
PWRGD
/PWRGD
MIC25XX-1
PWRGD
Active-High
MIC25XX-2
/PWRGD
Active-Low
OV
Threshold
ON
Turn-On Threshold
UV
Threshold
Pin Function
Power-Good Output: Open-drain. Asserted when the voltage on the DRAIN
pin (V
DRAIN
) is within V
PGTH
of VEE, indicating that the output voltage is
within proper specifications.
MIC2588-1 and MIC2594-1: PWRGD will be high-impedance when
V
DRAIN
is less than V
PGTH
, and will pull-down to V
DRAIN
when V
DRAIN
is
greater than V
PGTH
. Asserted State: Open-Drain.
Pin Description
Pin Number
1
1
1
MIC2588-2 and MIC2594-2: /PWRGD will pull-down to V
DRAIN
when
V
DRAIN
is less than V
PGTH,
and will be high impedance when V
DRAIN
is
greater than V
PGTH
. Asserted State: Active-Low.
2
MIC2588: Overvoltage Threshold Input. When the voltage at the OV pin is
greater than the V
OVH
threshold, the GATE pin is immediately pulled low by
an internal 100µA current pull-down.
MIC2594: Turn-On Threshold. At initial system power-up or after the device
has been shut off by the OFF pin, the voltage on the ON pin must exceed
the V
ONH
threshold in order for the MIC2594 to be enabled.
2
3
MIC2588: Undervoltage Threshold Input. When the voltage at the UV pin is
less than the V
UVL
threshold, the GATE pin is immediately pulled low by an
internal 100µA current pull-down. The UV pin is also used to cycle the device
off and on to reset the circuit breaker. Taken together, the OV and UV pins
form a window comparator which defines the limits of V
EE
within which the
load may safely be powered.
MIC2594: Turn-Off Threshold. When the voltage at the OFF pin is less than
the V
OFFL
threshold, the GATE pin is immediately pulled low by an internal
100µA current pull-down. The OFF pin is also used to cycle the device off
and on to reset the circuit breaker. Taken together, the ON and OFF pins
provide programmable hysteresis for the turn-on command voltage.
Negative Supply Voltage Input. Connect to the negative, or low side, terminal
of the input power supply.
Circuit Breaker Sense Input: The current-limit threshold is set by connecting
a resistor between this pin and V
EE
. When the current-limit threshold of
IR = 50mV is exceeded for an internal delay t
FLT
(400µs), the circuit breaker
is tripped and the GATE pin is immediately pulled low by I
GATEOFF
. Toggling
the UV/OFF pin will reset the circuit breaker. To disable the circuit breaker,
externally connect SENSE and VEE together.
Gate Drive Output: Connect to the gate of an external N-Channel MOSFET.
Drain Sense Input: Connect to the drain of an external N-Channel MOSFET.
Positive Supply Input. Connect to the positive, or high side, terminal of the
input power supply.
3
OFF
Turn-Off Threshold
4
5
VEE
SENSE
6
7
8
GATE
DRAIN
VDD
September 2005
3
M9999-083005
MIC2588/MIC2594
Micrel
Absolute Maximum Ratings
(1)
(All voltages are referred to V
EE
)
Supply Voltage (V
DD
– V
EE
) ...........................–0.3V to 100V
DRAIN, PWRGD pins ....................................–0.3V to 100V
GATE pin ......................................................–0.3V to 12.5V
SENSE, OV, UV, ON, OFF pins.........................–0.3V to 6V
Lead Temperature (soldering)
Standard package (-xBM)
(IR Reflow, Peak Temperature)........ 240°C +0°C/–5°C
Pb-Free Package-(xYM)
(IR Reflow, Peak Temperature)........ 260°C +0°C/–5°C
ESD Ratings
(3)
Human Body Model ................................................... 2kV
Machine Model ........................................................ 100V
Operating Ratings
(2)
Supply Voltage (V
DD
– V
EE
) .......................... +19V to +80V
Ambient Temperature Range
(T
A
) ................ –40°C to 85°C
Junction Temperature
(T
J
) ......................................... 125°C
Package Thermal Resistance
SOIC
(θ
JA
) ........................................................ 152°C/W
DC Electrical Characteristics
(4)
V
DD
= 48V, V
EE
= 0V, T
A
= 25°C, unless otherwise noted.
Bold
indicates specifications apply over the full operating temperature range
of –40°C to +85°C.
Symbol
V
DD
– V
EE
I
DD
V
TRIP
Parameter
Supply Voltage
Supply Current
Circuit Breaker Trip Voltage
GATE Pin Pull-up Current
GATE Pin Sink Current
GATE Drive Voltage, (V
GATE
– V
EE
)
SENSE Pin Current
UV Pin High Threshold Voltage
UV Pin Low Threshold Voltage
UV Pin Hysteresis
OV Pin High Threshold Voltage
OV Pin Low Threshold Voltage
OV Pin Hysteresis
ANSI ON Pin High Threshold
Voltage
ANSI OFF Pin Low Threshold
Voltage
Input Bias Current
(OV, UV, ON, OFF Pins)
Power-Good Threshold
Low-to-High transition
High-to-Low transition
V
UV
= 1.25V
High-to-Low transition
(V
DRAIN
– V
EE
)
1.1
1.26
1.198
1.198
Low-to-High transition
High-to-Low transition
1.198
1.165
V
GATE
= V
EE
to 8V
19V ≤ (V
DD
– V
EE
) ≤ 80V
V
TRIP
= V
SENSE
– V
EE
40
30
100
9
1.213
1.198
Condition
Min
19
3
50
45
230
10
0.2
1.243
1.223
20
1.223
1.203
20
1.223
1.223
1.247
1.247
0.5
1.40
1.247
1.232
1.272
1.247
11
Typ
Max
80
5
60
60
Units
V
mA
mV
µA
mA
V
µA
V
V
mV
V
V
mV
V
V
µA
V
I
GATEON
I
GATEOFF
V
GATE
V
UVH
V
UVL
(V
SENSE
– V
EE
) = 100mV
V
GATE
= 2V
V
SENSE
= 50mV
15V ≤ (V
DD
– V
EE
) ≤ 80V
I
SENSE
Low-to-High transition
High-to-Low transition
V
UVHYS
V
OVH
V
OVL
V
OVHYS
V
ONH
V
OFFH
I
CNTRL
V
PGTH
V
OLPG
PWRGD Output Voltage
V
OLPG
– V
DRAIN
(relative to voltage at the DRAIN pin) 0mA ≤ I
PG(LOW)
≤ 1mA
MIC25XX-1
MIC25XX-2
I
LKG(PG)
PWRGD Output Leakage Current
(V
DRAIN
– V
EE
) > V
PGTH
V
PWRGD
= V
DD
= 80V
(V
DRAIN
– V
EE
) < V
PGTH
–0.25
–0.25
0.8
0.8
1
V
V
µA
Notes:
1. Exceeding the “Absolute Maximum Ratings” may damage the devices.
2. The devices are not guaranteed to function outside the specified operating conditions.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model: 1.5kΩ in series with 100pF. Machine model: 200pF, no series
resistance.
4. Specification for packaged product only.
M9999-083005
4
September 2005
MIC2588/MIC2594
Micrel
Condition
Min
Typ
400
V
SENSE
– V
EE
= 100mV
1
1
1
1
R
PULLUP
= 100kΩ, C
LOAD
on PWRGD = 50pF
R
PULLUP
= 100kΩ, C
LOAD
on /PWRGD = 50pF
R
PULLUP
= 100kΩ, C
LOAD
on PWRGD = 50pF
1
1
2
2
3.5
Max
Units
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
AC Electrical Characteristics
(5)
Symbol
t
FLT
t
OCSENSE
t
OVPHL
t
OVPLH
t
UVPHL
t
UVPLH
t
PGL(1)
t
PGL(2)
t
PGH(1)
t
PGH(2)
Notes:
5. Specification for packaged product only.
6. Not 100% production tested. Parameters are guaranteed by design.
Parameter
Built-in Overcurrent Nuisance Trip
Time Delay
(6)
(Figure 1)
Overcurrent Sense to GATE Low
(Figure 2)
OV to GATE Low
(6)
(Figure 3)
OV to GATE High
(6)
(Figure 3)
UV to GATE Low
(6)
(Figure 4)
UV to GATE High
(6)
(Figure 4)
DRAIN High to PWRGD Output Low
(6)
(-1 Version parts only)
DRAIN Low to /PWRGD Output Low
(6)
(-2 Version parts only)
DRAIN Low to PWRGD Output High
(6)
(-1 Version parts only)
DRAIN High to /PWRGD Output High
(6)
R
PULLUP
= 100kΩ, C
LOAD
on /PWRGD = 50pF
(-2 Version parts only)
Timing Diagrams
OVERCURRENT
EVENT
I
LIMIT
I
LOAD
0A
t < t
FLT
t
t
FLT
Load current is regulated
at I
LIMIT
= 50mV/R
SENSE
Output OFF
(at V
DD
)
V
DRAIN
V
GATE
(V
EE
+10V)
(at V
EE
)
(at V
EE
)
Reduction in V
DRAIN
to support
I
LIMIT
= 50mV/R
SENSE
(at V
EE
)
Figure 1. Overcurrent Response
100mV
V
SENSE
- V
EE
t
OCSENSE
V
GATE
1V
Figure 2. SENSE to GATE LOW Timing Response
September 2005
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M9999-083005
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